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Universal Asynchronous Receiver Transmitter (UART)
Post: #1

Universal Asynchronous Receiver Transmitter (UART)

The Universal Asynchronous Receiver Transmitter (UART) is the most widely used serial data communication circuit ever. UARTs allow full duplex communication over serial communication links as RS232. UARTs are available as inexpensive standard products from many semiconductor suppliers, making it unlikely that this specific design is useful by itself.

The basic functions of a UART are a microprocessor interface, double buffering of transmitter data, frame generation, parity generation, parallel to serial conversion, double buffering of receiver data, parity checking, serial to parallel conversion. The data is transmitted asynchronously one bit at a time and there is no clock line.
The frame format of used by UARTs is a low start bit, 5-8 data bits, optional parity bit, and 1 or 2 stop bits. Universal Asynchronous Receive/Transmit consists of baud rate generator, transmitter and receiver. The number of bits transmitted per second is called baud rate and the baud rate generator generates the transmitter and receiver clocks separately. UART synchronizes the incoming bit stream with the local clock.

Transmitter interfaces to the data bus with the transmitter data register empty (TDRE) and write signals. When transmitting, UART takes eight bits of parallel data and converts it into serial bit stream and transmit them serially.
Receiver interfaces to the data bus with the receiver ready and the read signals. When UART detects the start bit, it receives the data serially and converts it into parallel form and when stop bit (logic high) is detected, data is recognized as a valid data.

UART Transmitter

The UART transmitter mainly consists of two eight bit registers the Transmit Data Register (TDR) and Transmit Shift Register (TSR) along with the Transmitter Control. The transmitter control generates the TDRE and TSRE signals which controls the data transmission through the UART transmitter. The write operation into the TDR is based on the signals generated from the microprocessor.
Post: #2
Universal Asynchronous Receiver Transmitter (UART)


1. UART Functionality
The UART is a universal asynchronous receiver/transmitter, which is modeled on the real-world
Intel® 8251 peripheral interface adapter component. In the model we are considering, the UART
consists of three main blocks.
• a serial transmit block
• a serial receive block and
• a CPU Interface (I/F) block.
The serial transmit block has two buffers (FIFO) into which data is written by the CPU I/F block.
After the data is written into the buffers it is transmitted serially onto TXD. As long as the FIFO
is not full the serial transmit block sets the signal TX_RDY high.
The serial receive block has four buffers (FIFO). The block checks for the parity and the validity
of the data frame on the RXD input and then writes correct data into its buffers. It also sets the
signal RX_RDY low if its FIFO is empty.

2. System partitioning and Component Description
The UART can be divided into several sub-components, according to different functionality.
The description of each of these components is given next section. The block diagram depicting
the more detailed component partitioning is shown in Figures 3 and 4.
The block diagram shows the different components. The D_XS, XCS, DATA, XWR, XRD
inputs are synchronized with the clock by their respective synchronizing blocks each of which
register the signals twice

2.1. The Components

DATASynch: This component registers the DATA signal twice so as to synchronize it with the
system clock CLK16M. The synchronized signal is data_bus1.

DXSSynch: This component registers the D_XS signal twice so as to synchronize it with the
system clock CLK16M. The synchronized output is DXS1.

XCSSynch: This component registers the XCS signal twice so as to synchronize it with the
system clock CLK16M. The synchronized output is XCS1.

XWRSynch: This component registers the XWR signal twice so as to synchronize it with the
system clock CLK16M. The synchronized output is X_WR.

XRDSynch: This component registers the XRD signal twice so as to synchronize it with the
system clock CLK16M. The synchronized output is X_RD.

RXDIFF: The RXD input is synchronized with the clock before being read by the receive block.
The synchronized output is r_xd.

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