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## Implementation of ScramblerDescrambler for use with SONETOTNPosted by: seminar class Created at: Tuesday 26th of April 2011 12:53:55 AM Last Edited Or Replied at :Tuesday 26th of April 2011 12:53:55 AM | vhdl scrambler x6 x6 1 ,
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domain • Long distance Tx • Stronger FEC • 3 layers OTS OTM OCh .................. [:=> Show Contents <=:] | |||

## Binary MultiplierPosted by: ajukrishnan Created at: Wednesday 09th of December 2009 06:00:49 AM Last Edited Or Replied at :Friday 18th of September 2015 03:41:28 AM | binary multiplier sequential ,
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radix-4 Modified Booth Algorithm (MBA), Wallace tree structure and Dadda tree structure. The design
is structured for an nxn multiplication. The MBA reduces the number of partial products or summands
by using the Carry-Save Adder (CSA). The Wallace tree structure serves to compress the partial
product terms by a ratio 3:2. The Dadda tree serves the same purpose with reduced hardware. To
enhance the speed of operation, Carry Look-Ahead (CLA) adders are used which is independent of the
number of bits of the two operands.Also implemented are combinations of dadda-booth and
wallace-booth Index .................. [:=> Show Contents <=:] | |||

## Implementation of stepper motor control using VHDL on FPGAPosted by: electronics seminars Created at: Tuesday 01st of December 2009 07:05:35 AM Last Edited Or Replied at :Wednesday 27th of July 2011 11:06:06 PM | FPGA ,
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e main aim of project is to control the stepper motor using the Very high speed integrated circuit
hardware description language. The main use of this project is to control the stepper motor in
antenna systems, floppy drives etc for high accuracy and efficiency..................[:=> Show Contents <=:] | |||

## DUAL PORT FIFOPosted by: computer science crazy Created at: Thursday 17th of September 2009 11:26:23 AM Last Edited Or Replied at :Saturday 08th of September 2012 06:34:39 PM | DUAL PORT FIFO ,
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ently for packet work. Although very useful in its basic form, the standard FIFO does lack two
attributes; autonomy and cascadability. Unfortunately you cannot simply connect two FIFOâ„¢s
together, as shown below, and expect them to automatically transfer data..................[:=> Show Contents <=:] | |||

## IMPLEMENTATION OF ADVANCED ENCRYPTION STANDARD AESPosted by: computer science crazy Created at: Wednesday 16th of September 2009 03:33:00 PM Last Edited Or Replied at :Wednesday 14th of March 2012 04:20:53 AM | STANDARD,
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e purpose, capable of achieving better performance than common software implementation. The proposed project AES is implemented by using VHDL. The device is operated at 100.29 MHz when targeted to Spartan 3E................... [:=> Show Contents <=:] | |||

## Multiplier Accumulator Component VHDL ImplementationPosted by: seminar projects crazy Created at: Friday 14th of August 2009 05:36:54 AM Last Edited Or Replied at :Thursday 23rd of February 2012 05:25:46 AM | Implementation ,
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prototyping enabler has also renewed interest in the FPGA architecture. The fine grain
reconfigurability of the FPGA architecture makes it an ideal candidate for use in system-on-chip
environments that strive to integrate heterogeneous programmable architectures..................[:=> Show Contents <=:] | |||

## Design of Manchester Encoder-decoder in VHDLPosted by: seminar projects crazy Created at: Friday 14th of August 2009 05:30:15 AM Last Edited Or Replied at :Sunday 13th of November 2011 10:07:10 PM | VHDL ,
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tute of Electrical and Electronics Engineers). The language has been through a few revisions, and
you will come across this in the VHDL community...................[:=> Show Contents <=:] | |||

## VHDL VHSIC Hardware Description LanguagePosted by: Computer Science Clay Created at: Thursday 30th of July 2009 05:46:09 AM Last Edited Or Replied at :Thursday 30th of July 2009 05:46:09 AM | Language ,
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. It was later revised in 1993. The 1993 revisions are minor and many of the simulation and
synthesis tools have not yet adopted them. It is an object-oriented language and therefore people
familiar with C++ or PASCAL can grasp it easily. VHDL can wear many hats. It is being used for
documentation, verification, and synthesis of large digital designs. This is actually one of the key
features of VHDL, since the same VHDL code can theoretically achieve all three of these goals, thus
saving a lot of effort. In addition to being used for each of these purposes, VHDL can be used to
take three diffe..................[:=> Show Contents <=:] |

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