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## Implementation of ScramblerDescrambler for use with SONETOTNPosted by: seminar class Created at: Tuesday 26th of April 2011 12:53:55 AM Last Edited Or Replied at :Tuesday 26th of April 2011 12:53:55 AM | vhdl scrambler x6 x6 1 ,
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ical signals in optical domain • Long distance Tx • Stronger FEC • 3 layers OTS OTM OCh .................. [:=> Show Contents <=:] | |||

## Binary MultiplierPosted by: ajukrishnan Created at: Wednesday 09th of December 2009 06:00:49 AM Last Edited Or Replied at :Tuesday 26th of July 2011 11:09:23 PM | binary multiplier sequential,
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ce tree, Dadda tree, Carry-save adder, Carry Look-Ahead adder...................[:=> Show Contents <=:] | |||

## Implementation of stepper motor control using VHDL on FPGAPosted by: electronics seminars Created at: Tuesday 01st of December 2009 07:05:35 AM Last Edited Or Replied at :Wednesday 27th of July 2011 11:06:06 PM | FPGA,
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TITLE : Implemen..................[:=> Show Contents <=:] | |||

## DUAL PORT FIFOPosted by: computer science crazy Created at: Thursday 17th of September 2009 11:26:23 AM Last Edited Or Replied at :Saturday 08th of September 2012 06:34:39 PM | DUAL PORT FIFO,
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DUAL PORT FIFO .................. [:=> Show Contents <=:] | |||

## IMPLEMENTATION OF ADVANCED ENCRYPTION STANDARD AESPosted by: computer science crazy Created at: Wednesday 16th of September 2009 03:33:00 PM Last Edited Or Replied at :Wednesday 14th of March 2012 04:20:53 AM | STANDARD ,
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s an approved cryptographic algorithm that can be used to protect electronic data. The AES algorithm
is a block cipher that can encrypt and decrypt digital information. The AES algorithm is capable of
using cryptographic keys of 128, 192, and 256 bits, and this project implements the 128 bit standard
using the VHDL, a hardware description language. The National Security Agency (NSA) announced that
AES-128 may be used for classified information at the SECRET level and AES-192/256 for TOP SECRET
level documents. The algorithm consists of four stages that make up a round which is iterated 10 t.................. [:=> Show Contents <=:] | |||

## Multiplier Accumulator Component VHDL ImplementationPosted by: seminar projects crazy Created at: Friday 14th of August 2009 05:36:54 AM Last Edited Or Replied at :Thursday 23rd of February 2012 05:25:46 AM | Implementation,
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and flip-flop level. Use of synthesis CAD tools to do this conversion, is becoming more widespread.
This is analogous to writing software programs in a high level language such as C, and then using a
compiler to convert the programs to machine language. The two most popular hardware description
languages are VHDL and Verilog. The MAC unit provides high-speed multiplication, multiplication with cumulative addition, multiplication with cumulative subtraction, saturation, and clear-to-zero functions. These operations are extensively used in Fast Fourier Transforms required by the MP3 Chip. Th.................. [:=> Show Contents <=:] | |||

## Design of Manchester Encoder-decoder in VHDLPosted by: seminar projects crazy Created at: Friday 14th of August 2009 05:30:15 AM Last Edited Or Replied at :Sunday 13th of November 2011 10:07:10 PM | VHDL,
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In addition to being used for each of these purposes, VHDL can be used to take three di.................. [:=> Show Contents <=:] | |||

## VHDL VHSIC Hardware Description LanguagePosted by: Computer Science Clay Created at: Thursday 30th of July 2009 05:46:09 AM Last Edited Or Replied at :Thursday 30th of July 2009 05:46:09 AM | Language ,
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three methods is employed. The following sections introduce you to the language by examining its
use for each of these three methodologies...................[:=> Show Contents <=:] |

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