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## Implementation of ScramblerDescrambler for use with SONETOTNPosted by: seminar class Created at: Tuesday 26th of April 2011 12:53:55 AM Last Edited Or Replied at :Tuesday 26th of April 2011 12:53:55 AM | vhdl scrambler x6 x6 1 ,
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-1 transitions • Scrambler is 7 bit self-synchronizing • .................. [:=> Show Contents <=:] | |||

## Binary MultiplierPosted by: ajukrishnan Created at: Wednesday 09th of December 2009 06:00:49 AM Last Edited Or Replied at :Tuesday 26th of July 2011 11:09:23 PM | binary multiplier sequential,
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independent of the number of bits of the two operands.Also implemented are combinations of
dadda-booth and wallace-booth Index Terms-Modified Booth Algorithm, Wallace tree, Dadda tree, Carry-save adder, Carry Look-Ahead adder................... [:=> Show Contents <=:] | |||

## Implementation of stepper motor control using VHDL on FPGAPosted by: electronics seminars Created at: Tuesday 01st of December 2009 07:05:35 AM Last Edited Or Replied at :Wednesday 27th of July 2011 11:06:06 PM | FPGA,
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per motor control using VHDL on FPGA. DESCRIPTION: The main aim of project is to control the stepper motor using the Very high speed integrated circuit hardware description language. The main use of this project is to control the steppe.................. [:=> Show Contents <=:] | |||

## DUAL PORT FIFOPosted by: computer science crazy Created at: Thursday 17th of September 2009 11:26:23 AM Last Edited Or Replied at :Saturday 08th of September 2012 06:34:39 PM | DUAL PORT FIFO,
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dard FIFO does lack two attributes; autonomy and cascadability. Unfortunately you cannot simply
connect two FIFOâ„¢s together, as shown below, and expect them to automatically transfer data..................[:=> Show Contents <=:] | |||

## IMPLEMENTATION OF ADVANCED ENCRYPTION STANDARD AESPosted by: computer science crazy Created at: Wednesday 16th of September 2009 03:33:00 PM Last Edited Or Replied at :Wednesday 14th of March 2012 04:20:53 AM | STANDARD ,
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ecific applications. At backbone communication channels, or at heavily loaded server, it is not
possible to lose processing speed running cryptography algorithms in general software, which drops
the efficiency of the overall system. On the other side, a low cost and small design can be used in
smart card applications, allowing a wide range of equipment to operate securely. The design goal of this project is to create a demonstration of the AES-128 for the end user and not for integration into a communication or data storage device; however this design could be modified to such ends. The mai.................. [:=> Show Contents <=:] | |||

## Multiplier Accumulator Component VHDL ImplementationPosted by: seminar projects crazy Created at: Friday 14th of August 2009 05:36:54 AM Last Edited Or Replied at :Thursday 23rd of February 2012 05:25:46 AM | Implementation,
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nd as a rapid prototyping enabler has also renewed interest in the FPGA architecture. The fine grain
reconfigurability of the FPGA architecture makes it an ideal candidate for use in system-on-chip
environments that strive to integrate heterogeneous programmable architectures..................[:=> Show Contents <=:] | |||

## Design of Manchester Encoder-decoder in VHDLPosted by: seminar projects crazy Created at: Friday 14th of August 2009 05:30:15 AM Last Edited Or Replied at :Sunday 13th of November 2011 10:07:10 PM | VHDL,
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VHDL is an acronym which stands for VHSIC Hardware Description Language. VHSIC is yet another acronym which stands for Very High Speed Integrated Circuits VHDL can wear many hats. It is being used for documentation, verification, and synthesis of large digital designs. This is actually one of the key features of VHDL, since the same VHDL code can theoretically achieve all three of these goals, thus saving a lot of effort. In addition to being used for each of these purposes, VHDL can be used to take three different approaches to describing hardware. These three different approaches are.................. [:=> Show Contents <=:] | |||

## VHDL VHSIC Hardware Description LanguagePosted by: Computer Science Clay Created at: Thursday 30th of July 2009 05:46:09 AM Last Edited Or Replied at :Thursday 30th of July 2009 05:46:09 AM | Language ,
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m of the US Department of Defense. The department organized a work shop in 1981 to lay down the
specifications of a language which could describe hardware at various levels of abstractions, could
generate test signals and record responses, and could act as a medium of information exchange
between the chip foundries and the CAD tool operators. However, due to military restrictions, it
remained classified till 1985. There was a large participation of the private sector electronics industry in the development of the language. It felt that there was a need to make the language industr.................. [:=> Show Contents <=:] |

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