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## Implementation of ScramblerDescrambler for use with SONETOTNPosted by: seminar class Created at: Tuesday 26th of April 2011 12:53:55 AM Last Edited Or Replied at :Tuesday 26th of April 2011 12:53:55 AM | vhdl scrambler x6 x6 1 ,
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IM OF THE PROJECT • This project deals with design of scramblers/ descramblers for use with SONET and OTN optical networks. • Writing VHDL code for scrambler/ descrambler and performing synthesis and simulation on FPGA. ABOUT FPGA• FPGA • FPGA SERIES FAMILY NAME DEVICE NAME PACKAGE SPEED SCRAMBLING• Used for sufficent 0-1 transitions • Scrambler is 7 bit self-synchronizing • Polynomial X7 + X6 + 1 • Scrambler is initialized with ones SONET• Bellcore 1985 • ITU-T Standard • 2 sides of SONET • 3 layer.................. [:=> Show Contents <=:] | |||

## Binary MultiplierPosted by: ajukrishnan Created at: Wednesday 09th of December 2009 06:00:49 AM Last Edited Or Replied at :Tuesday 26th of July 2011 11:09:23 PM | binary multiplier sequential ,
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Look-Ahead (CLA) adders are used which is independent of the number of bits of the two
operands.Also implemented are combinations of dadda-booth and wallace-booth Index Terms-Modified Booth Algorithm, Wallace tree, Dadda tree, Carry-save adder, Carry Look-Ahead adder................... [:=> Show Contents <=:] | |||

## Implementation of stepper motor control using VHDL on FPGAPosted by: electronics seminars Created at: Tuesday 01st of December 2009 07:05:35 AM Last Edited Or Replied at :Wednesday 27th of July 2011 11:06:06 PM | FPGA ,
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TITLE : Implementation of stepper motor control using VHDL on FPGA.
DESCRIPTION: The main aim of project is to control the stepper motor using the Very high speed integrated circu.................. [:=> Show Contents <=:] | |||

## DUAL PORT FIFOPosted by: computer science crazy Created at: Thursday 17th of September 2009 11:26:23 AM Last Edited Or Replied at :Saturday 08th of September 2012 06:34:39 PM | DUAL PORT FIFO ,
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r packet work. Although very useful in its basic form, the standard FIFO does lack two attributes;
autonomy and cascadability. Unfortunately you cannot simply connect two FIFOâ„¢s together, as
shown below, and expect them to automatically transfer data..................[:=> Show Contents <=:] | |||

## IMPLEMENTATION OF ADVANCED ENCRYPTION STANDARD AESPosted by: computer science crazy Created at: Wednesday 16th of September 2009 03:33:00 PM Last Edited Or Replied at :Wednesday 14th of March 2012 04:20:53 AM | STANDARD,
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tographic keys of 128, 192, and 256 bits, and this project implements the 128 bit standard using the
VHDL, a hardware description language. The National Security Agency (NSA) announced that AES-128 may
be used for classified information at the SECRET level and AES-192/256 for TOP SECRET level
documents. The algorithm consists of four stages that make up a round which is iterated 10 times for a 128-bit length key, 12 times for a 192-bit key, and 14 times for a 256-bit key. The first stage SubBytes transformation is a non-linear byte substitution for each byte of the block. The second stage.................. [:=> Show Contents <=:] | |||

## Multiplier Accumulator Component VHDL ImplementationPosted by: seminar projects crazy Created at: Friday 14th of August 2009 05:36:54 AM Last Edited Or Replied at :Thursday 23rd of February 2012 05:25:46 AM | Implementation ,
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language allows a digital system to be designed and debugged at a higher level before conversion to
the gate and flip-flop level. Use of synthesis CAD tools to do this conversion, is becoming more
widespread. This is analogous to writing software programs in a high level language such as C, and
then using a compiler to convert the programs to machine language. The two most popular hardware
description languages are VHDL and Verilog. The MAC unit provides high-speed multiplication, multiplication with cumulative addition, multiplication with cumulative subtraction, saturation, and clear-to-z.................. [:=> Show Contents <=:] | |||

## Design of Manchester Encoder-decoder in VHDLPosted by: seminar projects crazy Created at: Friday 14th of August 2009 05:30:15 AM Last Edited Or Replied at :Sunday 13th of November 2011 10:07:10 PM | VHDL ,
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VHDL is a standard (VHDL-1076) developed by IEEE (Institute of Electrical and Electronics Engineers). The language has been through a few revisions, and you will come across this in the VHDL community................... [:=> Show Contents <=:] | |||

## VHDL VHSIC Hardware Description LanguagePosted by: Computer Science Clay Created at: Thursday 30th of July 2009 05:46:09 AM Last Edited Or Replied at :Thursday 30th of July 2009 05:46:09 AM | Language ,
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e description. Most of the time a mixture of the three methods is employed. The following sections
introduce you to the language by examining its use for each of these three methodologies...................[:=> Show Contents <=:] |

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