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Title: area efficient airthmetic expression evaluation using floating point cores
Page Link: area efficient airthmetic expression evaluation using floating point cores -
Posted By: nagaraju burla
Created at: Tuesday 16th of February 2010 12:50:56 AM
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Title: A High-Speed Compressor for Double-Precision Floating-Point Data
Page Link: A High-Speed Compressor for Double-Precision Floating-Point Data -
Posted By: project report tiger
Created at: Wednesday 10th of February 2010 11:27:55 AM
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Many scientific programs exchange large quantities of double-precision data between processing nodes and with mass storage devices. Data compression can reduce the number of bytes that need to be transferred and stored. However, data compression is only likely to be employed in high-end computing environments if it does not impede the throughput. This paper describes and evaluates FPC, a fast lossless compression algorithm for linear streams of 64-bit floating-point data. FPC works well on hard-to-compress scientific data sets and meets the thr ....etc

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Title: Floating-Point FPGA Architecture and Modeling
Page Link: Floating-Point FPGA Architecture and Modeling -
Posted By: seminar-database
Created at: Thursday 19th of May 2011 05:06:04 AM
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Floating-Point FPGA: Architecture and Modeling
An architecture for a reconfigurable device that is specifically optimized for floating-point applications is described in this article. The control logic and bit-oriented operations are implemented by the fine grained units and the parameterized and reconfigurable word-based lookup tables etc are implemented by the coarse grained units. These implement the lookup tables and the floating point operations as well as to implemen the data paths. the virtual embedded block scheme is described w ....etc

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Title: free download vhdl code for floating point division
Page Link: free download vhdl code for floating point division -
Posted By: Guest
Created at: Sunday 18th of November 2012 02:50:59 AM
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please send to [email protected] ....etc

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Title: FFTIFFT Block Floating Point Scaling
Page Link: FFTIFFT Block Floating Point Scaling -
Posted By: seminar details
Created at: Tuesday 05th of June 2012 06:45:08 AM
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FFT/IFFT Block Floating Point Scaling




Introduction

The Altera® FFT MegaCore® function uses block-floating-point (BFP)
arithmetic internally to perform calculations. BFP architecture is a
trade-off between fixed-point and full floating-point architecture.
Unlike an FFT block that uses floating point arithmetic, a
block-floating-point FFT block does not provide an input for exponents.
Internally, a complex value integer pair is represented with a si ....etc

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Title: Prenormalization Rounding in IEEE Floating-Point Operations Using a Flagged Prefix Ad
Page Link: Prenormalization Rounding in IEEE Floating-Point Operations Using a Flagged Prefix Ad -
Posted By: seminar topics
Created at: Sunday 14th of March 2010 12:29:36 PM
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Prenormalization Rounding in IEEE Floating-Point Operations Using a Flagged Prefix Adder,
This paper demonstrates howIEEE 754 floating-point standard compliant rounding can be merged with carry-propagate addition in floating-point unit (FPU) designs by using a novel adaptation of the prefix adder. The paper considers add/subtract, multiply, and SRT divide operations and demonstrates that in every case a generic rounding architecture based on a prefix adder with a small amount of additional logic is sufficient to cover all the rounding modes. ....etc

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Title: DESIGN OF A HIGH-SPEED SPECTRAL SIGNAL PROCESSING SYSTEM WITH A FLOATING-POINT DSP FO
Page Link: DESIGN OF A HIGH-SPEED SPECTRAL SIGNAL PROCESSING SYSTEM WITH A FLOATING-POINT DSP FO -
Posted By: Zigbee
Created at: Sunday 05th of September 2010 03:03:12 AM
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SEMINAR ON
DESIGN OF A HIGH-SPEED SPECTRAL SIGNAL PROCESSING SYSTEM WITH A FLOATING-POINT DSP FOR FT-IR SPECTROMETER



SUBMITTED BY:
ANOOP E M
ROLL NO: 11
S7T2


ABSTRACT
In this seminars paper, DESIGN OF A HIGH SPEED SIGNAL PROCESSING SYSTEM WITH A FLOATING-POINT DSP FOR FTIR SPECTROMETER a new Spectral Signal Processing System (SSPS), which uses a high-speed floating-point digital signal processor (DSP) as its central processor, is presented. The main application of the system is in Fourier transform i ....etc

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Title: vhdl code for division algorithm
Page Link: vhdl code for division algorithm -
Posted By: Guest
Created at: Tuesday 16th of October 2012 07:12:08 AM
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Title: Architectural modifications to enhance the floating point performance of FPGA
Page Link: Architectural modifications to enhance the floating point performance of FPGA -
Posted By: science projects buddy
Created at: Saturday 25th of December 2010 10:14:38 PM
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ARCHITECTURAL MODIFICATIONS TO ENHANCE THE FLOATING-POINT PERFORMANCE OF FPGA
Seminar Report
by
ABHIJITH.M.A
DEPARTMENT OF ELECTRONICS AND COMMUNICATION
COLLEGE OF ENGINEERING
THIRUVANANTHAPURAM
2010



ABSTRACT

With latest technologies FPGAs have reached the point where they are capable of implementing complex floating-point applications. However the application of FPGA for scientific applications that require floating point operations is limited .In that ....etc

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Title: DESIGN VERIFICATION AND SYNTHESIS OF FLOATING POINT ARITHMETIC UNIT
Page Link: DESIGN VERIFICATION AND SYNTHESIS OF FLOATING POINT ARITHMETIC UNIT -
Posted By: seminar class
Created at: Monday 02nd of May 2011 03:46:24 AM
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1. INTRODUCTION
An arithmetic-logic unit (ALU) is the part of a computer processor (CPU) that carries out arithmetic and logic operations on the operands in computer instruction words. In some processors, the ALU is divided into two units, an arithmetic unit (AU) and a logic unit (LU). Some processors contain more than one AU - for example, one for fixed-point operations and another for floating-point operations.
Generally ar ....etc

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