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CARBON NANOTUBES FOR VLSI INTERCONNECT AND TRANSISTOR APPLICATIONS


Posted by: seminar addict
Created at: Tuesday 31st of January 2012 05:18:11 AM
Last Edited Or Replied at :Tuesday 31st of January 2012 05:18:11 AM
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e to manipulate the Nanotubes in a controlled way. IBM researchers using an atomic force microscope (AFM), an instrument whose tip can apply accurately measured forces to atoms and molecules, have recently devised a means of changing a nanotube's position, shape and orientation, as well as cutting it


BASIC STRUCTURE OF NANOTUBES


Nanotubes are members
of the fullerene structural
family, which also includes
the spherical bucky balls.

Their name is derived from
their size, since the diameter
of a Nanotube is of the order
of a few nanometers, while
they can be up to ..................[:=> Show Contents <=:]



A New VLSI Architecture of Parallel MultiplierAccumulator Based on Radix-2 Modified


Posted by: smart paper boy
Created at: Saturday 30th of July 2011 02:30:06 AM
Last Edited Or Replied at :Saturday 30th of July 2011 02:30:06 AM
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n. It is possible to decompose multipliers into two parts. The first part is dedicated to the generation of partial products, and the second one collects and adds them.
The basic multiplication principle is two fold i.e. evaluation of partial products and accumulation of the shifted partial products. It is performed by the successive additions of the columns of the shifted partial product matrix. The ‘multiplier’ is successfully shifted and gates the appropriate bit of the ‘multiplicand’. The delayed, gated instance of the multiplicand must all be in the same column of the shifted par..................[:=> Show Contents <=:]



mechanical engineering research topics and papers


Posted by: project topics
Created at: Monday 09th of May 2011 12:18:04 AM
Last Edited Or Replied at :Monday 19th of November 2012 03:36:02 AM
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93. Laser Drilling Of Cooling Holes for Aeroengine Components
94. Breast Implant Surface Development
95. Design Optimisation & Health Monitoring Techniques for Composite Structures
96. Thermoacoustic Technologies for Energy and Building
97. Heat transfer in magnetic liquids
98. An Investigation of Tool Chip Contact Length and Phenomena in High Speed Turning Using Uncoated and Coated Tools
99. The Modeling and Practice of Multiple Track Laser Direct Metal Deposition (LDMD) -
100. Three-Dimensional Imaging for Atomisation & Sprays
101. Combined Laser and Mechanical Micro-Drilling of N..................[:=> Show Contents <=:]



VLSI Physical Design Automation ppt


Posted by: seminar surveyer
Created at: Thursday 27th of January 2011 03:22:48 AM
Last Edited Or Replied at :Thursday 27th of January 2011 03:22:48 AM
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rtitions are balanced.

Number of partitions: The number of partitions appears as a constraint in the partitioning problem at system level and board level partitioning. This prevents a system from having too many PCBs and a PCB from having too many chips. A large number of partitions may ease the design of individual partitions but they may also increase the cost of fabrication and the number of interconnections between the partitions. At the same time, if the number of partitions is small, the design of these partitions might still be too complex to be handled efficiently. At chip level, th..................[:=> Show Contents <=:]



research topics in computer science and engineering


Posted by: project topics
Created at: Saturday 22nd of January 2011 03:44:52 AM
Last Edited Or Replied at :Saturday 26th of February 2011 12:08:07 PM
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ied Model Key Agreement Protocols
28. A System For Automatic Eva..................[:=> Show Contents <=:]



vlsi technology based seminars


Posted by: [email protected]
Created at: Monday 20th of September 2010 11:36:57 PM
Last Edited Or Replied at :Monday 28th of January 2013 11:08:16 PM
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hi i needed more vlsi ..................[:=> Show Contents <=:]



Optical Interconnects


Posted by: project topics
Created at: Saturday 03rd of April 2010 09:10:33 AM
Last Edited Or Replied at :Saturday 09th of July 2011 05:03:43 AM
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S,Parallel optical interfaces can be conceived that consist of arrays of optoelectronic devices of the order of one thousand optical channels each 'running at speeds around I Gbit/s and hence offering and overall capacity of 1 Gbit/s to a single integrated circuit. Although there are still unresolved difficulties in the areas of architectural design, manufacturing processes, simulation and packaging (as explained later), the technology has now developed to the point that it is possible to contemplate its use in commercial systems within a time-frame of 5-10 years. Fig 1st shows the concept of ..................[:=> Show Contents <=:]



low power design in vlsi


Posted by: meghasb
Created at: Friday 06th of November 2009 05:22:01 AM
Last Edited Or Replied at :Tuesday 21st of September 2010 05:59:37 AM
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pls send me pdf ..................[:=> Show Contents <=:]



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